1. Field of the Invention
This invention relates to CMOS output buffers, and more particularly to low-noise and impedance-adjusting output buffers.
2. Description of the Related Art
Complementary metal-oxide-semiconductor (CMOS) circuits are often used as interface or "glue" logic for digital systems. Higher-performance systems require increased speed and current requirements for the glue logic. Higher current drive increases speed because load capacitances are more quickly charged or discharged. Unfortunately, unwanted noise often increases too.
CMOS chips with higher-drive output buffers often produce a type of noise known as ground bounce, due to rapid changes in current through the parasitic inductances of the integrated circuit (IC) package. These inductances resist changes in current by changing the voltages on power or ground supplies. Such voltage changes can falsely trigger logic within the IC device, or other devices in the system.
The rate of voltage change of the output, the edge rate, increases for these faster devices. The high edge rate can reflect off the ends of printed-circuit-board (PCB) wiring traces driven by the output buffer. These reflections produce voltage variations known as undershoot, overshoot, and ringing (oscillation). Careful layout of these wiring traces is needed to minimize trace-ends that can cause reflections. Termination devices such as resistors to ground at the ends of the traces are often used to absorb the reflection-causing wave front produced by the high edge rate.
Dampening resistors are sometimes used. Dampening resistors are resistors in series on the wiring trace rather than to power or ground. Dampening resistors reduce or slow down the high edge rate as well as any reflections. While discrete dampening resistors are often used, the output buffer itself provides some impedance, which also acts as a dampening resistor. Unfortunately, this impedance decreases with higher-current-drive output buffers. The lower impedance of these output buffers creates a greater mismatch between the output buffer's impedance and the impedance of the wiring trace.
Power budgets also limit the quality of termination. Lower-impedance resistors consume much power. CMOS chips driving terminated lines can only sink or source a limited amount of current in the static or D.C. state. The D.C. current specifications of CMOS chips, known as IOL and IOH, are usually not large enough for termination resistors smaller than 100 or 50 ohms. Better termination could be obtained if 10 or 20-ohm resistors were used for termination.
FIG. 1 is a diagram of a waveform of a prior-art high-drive output buffer driving a PCB wiring trace. The high current drive of the output buffer produces a high edge rate that rapidly changes the output voltage from ground to the power-supply voltage, Vcc. The high edge rate produces a wave front that travels down the wiring trace and reflects off one or more ends. The reflected wave front then travels back up the wiring trace to the output buffer, and raises the voltage at the output buffer when the reflected wave arrives. The raised voltage is above Vcc and is known as an overshoot. This reflected wave then reverses direction and travels back to the end of the wiring trace, is reflected, and again reaches the output buffer, producing a series of both overshoots and undershoots, known as ringing. Since the reflected wave is dampened and loses energy at each reflection, the amplitude of the ringing gradually decreases. Low-going ringing (undershoot) is caused by a mis-match in impedance. Multiple reflections interfere with each other and cause the ringing.
When the output buffer switches from high to low, another high-edge rate wave travels down the wiring trace and is reflected back, producing undershoot and more ringing. This undershoot can cause ground bounce inside the output buffer's IC.
When the ringing and over/undershoot is large, logic can read a static signal as low when the static signal is actually high. For example, a static 3-volt signal input to another pin of the IC is a high signal, but when the internal ground of the IC bounces up from 0 volt to 2 volt, the static 3-volt signal appears to be a 1-volt signal, a low input. When the input signal is connected to a latch or flip-flop, the false low can be latched in, causing an error. Thus noise is a serious problem.
Several prior-art solutions to these problems are known. For example, Pierce et al., U.S. Pat. No. 5,319,252, assigned to Xilinx Inc. of San Jose, Calif., discloses an output buffer which gradually turns output buffers on and off so that there is no sharp discontinuity in the current flow. The output voltage is fed back to gradually turn off the output buffer at the end of the voltage transition. Lipp in U.S. Pat. No. 5,347,177, discloses a closed-loop trace which is driven by output buffers with level-sensitive impedance control.
Prior Art Pulses Large Drivers On
Sharpe-Geisler, U.S. Pat. No. 5,438,277, assigned to Advanced Micro Devices of Sunnyvale, Calif., discloses an output buffer using two pull-down devices. A noisy (larger) pull-down device is connected to a noisy ground (having ground bounce) while a quiet (smaller) pull-down device is connected to a quiet ground. A one-shot triggered by an internal signal first switches on the noisy pull-down, then turns off the noisy pull-down and turns on the quiet pull-down. Kang, U.S. Pat. No. 5,410,262, assigned to Samsung, is a similar approach.
FIG. 2 is a prior-art output buffer that pulses a larger driver on during an output transition. When a clock CLK is active, NAND gates 20, 22 pass through an input DIN and its complement .about.DIN. When DIN is high, inverter 24 drives the gate of pull-up transistor 12 high, which pulls output DOUT high. Nodes PD1 driving the gate of large pull-down transistor 14, and node PD2 driving the gate of small pull-down transistor 16, are both low.
When DIN switches low, NAND gate 22 outputs a low which is immediately propagated to the upper input NOR gate 26. Node PD2, the lower input of NOR gate 26, is still low, because the change in .about.DIN has not yet propagated through inverting delay chain 18. Since both inputs to NOR gate 26 are temporarily low, node PD1 is high, turning on large pull-down transistor 14. However, the low on node PD2 keeps smaller pull-down transistor 16 off. After the change in .about.DIN propagates through inverting delay chain 18, node PD2 becomes high, turning on smaller pull-down transistor 16, while turning off larger pull-down transistor 14 by the high input on NOR gate 26.
FIG. 3 is a timing diagram for the prior-art buffer of FIG. 2 showing that the larger pull-down transistor is pulsed on. When DIN goes low, node PD1 is pulsed on for a short time. The larger pull-down transistor rapidly changes the output voltage DOUT. However, the pulse on node PD1 ends before the voltage swing is complete to reduce ringing. Then the smaller pull-down transistor, driven by node PD2, completes the output voltage swing. The width of the pulse for PD1 is usually targeted for worst-case conditions of ground bounce, which is high Vcc and cold temperature.
While pulsing the larger pull-down transistor on and off during the output voltage transition is useful in reducing undershoot ground bounce, the D.C. current is limited to the current from the smaller pull-down transistor, since the larger transistor is only on during the output transition, not in static conditions. The lower D.C. current limits the impedance of the termination resistors, degrading termination.
When a CMOS chip has several outputs, sometimes one output's slewing can disrupt other outputs that are not changing. Especially when several outputs change at the same time is the problem of undershoot most severe.
What is desired is an output buffer with high current drive and high speed. It is desired to reduce noise from the fast edge rate, such as ringing, undershoot, overshoot, and ground bounce. It is desired to dynamically control the impedance of the output buffer to provide low impedance as the output voltage is rapidly changing, but high impedance when the reflected wave front is received to dampen the reflections. It is also desired to leave the larger drivers on during static periods to provide strong IOH and IOL output currents but have these drivers turn off during the critical ringing period. It is further desired to disable neighboring pins' output buffers when one output buffer switches to prevent noise coupling into other pin's outputs.